Advanced VLSI Design | EveryEng

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Self-paced Advanced

Advanced VLSI Design

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FREE

1593 min

Anytime

English

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Team EveryEngMechanical Engineering

Electronics & Instrumentation

Electrical Engineering

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Why enroll

Participants join the Advanced VLSI Design course to gain specialized skills required for careers in the fast-growing semiconductor industry. The course helps learners understand advanced chip design concepts, modern VLSI methodologies, and industry-standard design practices. It enables engineers and students to build expertise in high-performance and low-power integrated circuit design while enhancing their job prospects in VLSI, ASIC, FPGA, and semiconductor companies. The knowledge gained also prepares participants for advanced research, higher studies, and emerging technologies in electronics.

Your instructor

Team EveryEng

Engineer

Mechanical Engineering

22+ yrs experience·India

Is this course for you?

You should take this if

You work in Electronics & Instrumentation
You're a Electrical Engineering / Electronics & Telecommunication professional
You have 3+ years of hands-on experience in this field
You prefer self-paced learning you can revisit

You should skip if

You're new to this field with no prior experience
You need a different specialisation outside Electrical Engineering
You need live interaction with an instructor

Course details

The Advanced VLSI Design course provides an in-depth understanding of modern Very Large Scale Integration (VLSI) design methodologies used in semiconductor and integrated circuit development. It covers advanced CMOS design principles, digital circuit optimization, and high-performance chip design techniques. Learners will explore timing analysis, power optimization, clock distribution, and physical design challenges. The course also explains design automation tools, layout strategies, and verification methodologies used in the VLSI industry. Real-world design constraints and trade-offs are discussed to help students understand practical chip development. Topics such as interconnect modeling, signal integrity, low-power design, and testing techniques are covered in detail. Designed by expert faculty from IIT Bombay, the course combines theoretical concepts with engineering applications. It is ideal for electronics and electrical engineering students, VLSI enthusiasts, and semiconductor professionals seeking advanced knowledge. By the end of the course, learners will be equipped with the skills required to design, analyze, and optimize complex integrated circuits for modern electronic systems.

Course suitable for

Key topics covered

Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design
Historical Perspective and Future Trends in CMOS VLSI Circuit – Part II
Logical Effort: A Way of Designing Fast CMOS Circuits
Logical Effort: Designing Fast CMOS Circuits – Continued
Logical Effort: Designing Fast CMOS Circuits – Part III
Power Estimation and Control in CMOS VLSI Circuits
Power Estimation and Control in CMOS VLSI Circuits – Continued
Low Power Design Techniques
Low Power Design Techniques – Part II
Arithmetic Implementation Strategies for VLSI
Arithmetic Implementation Strategies for VLSI – Part II
Arithmetic Implementation Strategies for VLSI – Part III
Arithmetic Implementation Strategies for VLSI – Part IV
Interconnect-Aware Design: Impact of Scaling, Buffer Insertion, and Inductive Peaking
Interconnect-Aware Design: Low Swing and Current-Mode Signaling
Interconnect-Aware Design: Capacitively Coupled Interconnects
Introduction to Hardware Description Languages (HDL)
Managing Concurrency and Time in Hardware Description Languages
Introduction to VHDL
Basic Components in VHDL
Structural Description in VHDL
Behavioral Description in VHDL
Introduction to Verilog
FSM + Datapath (GCD Example)
FSM + Datapath (Continued)

Course content

The course is readily available, allowing learners to start and complete it at their own pace.

25 lectures26 hr 33 min

Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design
53 min
Historical Perspective and Future Trends in CMOS VLSI Circuit – Part II
102 min
Logical Effort: A Way of Designing Fast CMOS Circuits
66 min
Logical Effort: Designing Fast CMOS Circuits – Continued
72 min
Logical Effort: Designing Fast CMOS Circuits – Part III
75 min
Power Estimation and Control in CMOS VLSI Circuits
60 min
Power Estimation and Control in CMOS VLSI Circuits .
79 min
Low Power Design Techniques
54 min
Low Power Design Techniques -Part II
111 min
Arithmetic Implementation Strategies for VLSI
57 min
Arithmetic Implementation Strategies for VLSI – Part II
59 min
Arithmetic Implementation Strategies for VLSI – Part III
109 min
Arithmetic Implementation Strategies for VLSI – Part IV
95 min
Interconnect aware design: Impact of scaling, buffer insertion and inductive peaking
53 min
Interconnect aware design: Low swing and Current Mod-e signaling
53 min
Interconnect aware design: capacitively coupled interconnects
49 min
Introduction to Hardware Description Languages
51 min
Managing concurrency and time in Hardware Description Languages
53 min
Introduction to VHDL
52 min
Basic Components in VHDL
51 min
Structural Description in VHDL
21 min
Behavioral Description in VHDL
51 min
Introduction to Verilog
55 min
FSM + datapath (GCD example)
58 min
FSM + datapath (continued)
54 min

Opportunities that await you!

Career opportunities

Why people choose EveryEng

Industry-aligned courses, expert training, hands-on learning, recognized certifications, and job opportunities-all in a flexible and supportive environment.

What learners say about this course

Ayshwarya Mahadevan Engineer

Jan 27, 2026

good

viren prajapati piping stress engineer

Jan 19, 2026

.

sandeep saroj

Jan 4, 2026

Valuable content

Dipansh Sharma Mechanical Design Intern

May 3, 2026

Nice change of pace to see edge cases treated like first-class citizens instead of footnotes, especially for a beginner/intermediate Solidworks track. The moment that stuck was the section on the bolt lug geometry where he intentionally breaks the fillet, runs interference, then walks back tolerances; that’s the kind of thing that shows up later in prod and costs a PR. I’ve shipped CAD that looked fine in a repo but blew up at assembly, so the emphasis on mates failing felt real. The pacing mostly worked, though I wasn’t sold on how quickly configs were introduced; a bit more time on why one config beats another would help. still, the way he frames failure modes and stress paths maps cleanly to how I think about arch and CI checks in infra, even if you’re not building rifles. That framing alone made the time worthwhile between meetings.

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