Electronic Systems Design: Hands-on Circuits and PCB Design with CAD Software | EveryEng

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Electronic Systems Design: Hands-on Circuits and PCB Design with CAD Software

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1752 min

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Electronics & Instrumentation

Electronics & Telecommunication

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Why enroll

Participants join this course to learn how electronic circuits are actually designed and built in practice. It helps them move from theory to real hardware by giving hands-on experience with PCB design and industry-used tools. This course is ideal for anyone who wants practical skills for projects, research, or a career in electronics

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Engineering Academy

Engineer

Learn Without Limits: Free Engineering Courses

5+ yrs experience·India

Is this course for you?

You should take this if

You work in Electronics & Instrumentation
You're a Electronics & Telecommunication / CAD & Analysis professional
You have 3+ years of hands-on experience in this field
You want to build skills in Engineering & Design, Project Management

You should skip if

You're new to this field with no prior experience
You need a different specialisation outside Electronics & Telecommunication
You need live interaction with an instructor

Course details

This course focuses on building a strong practical foundation in electronic circuits and printed circuit board (PCB) design. Participants learn the fundamentals of analog and digital circuits and how these circuits are implemented in real hardware. The course covers the complete PCB design flow, starting from schematic entry to PCB layout, routing, and final fabrication files. Learners work hands-on with popular CAD and simulation tools such as CircuitMaker and circuit simulators to design and verify their circuits. Practical sessions include creating PCB footprints, working with through-hole and via connections, and applying proper routing techniques. Participants also learn how to assemble PCBs, solder components, and test circuit functionality. Emphasis is given to real-world design practices, common mistakes, and debugging methods. By the end of the course, learners can confidently design, build, and test functional electronic systems.

Source: Nptel IIT Delhi [Youtube Channel]

Course suitable for

Key topics covered

Intro
Passive Circuit Elements: R, L and C
Resistor color coding, surface mount capacitors and inductors on PCBs
Active Circuit Elements: MOSFET, BJTs
Network Analysis: Kirchhoff's Laws
Network Theorems: Thevenin, Norton, Maximum Power Transfer, etc.
Circuit simulations using SPICE: Operating point analysis
DC simulations and importing third-party models
Small-signal simulations, transient simulations
PCB substrate
Interconnect design
CMOS inverter basics
CMOS inverter design
Combinational circuit design: Part 1
Combinational circuit design: Part 2
Dynamic logic circuit design
Sequential logic circuit design
Digital design: Boolean algebra
Logic families, component datasheets
TTL / CMOS logic interfacing constraints
Hardware description languages: VHDL and Verilog
Introduction to Verilog simulation software
Combinational circuit simulation using iVerilog
Adders, multiplexer simulation using iVerilog
High-speed PCBs
Signal integrity in PCBs
Signal crosstalk, skews and jitter in PCBs
KiCad software workflow
KiCad design modules

Course content

The course is readily available, allowing learners to start and complete it at their own pace.

30 lectures29 hr 12 min

Intro
2 min
Introduction
68 min
Passive Circuit Elements : R, L and C
57 min
Resistor color coding, Surface mount capacitors and inductors on PCBs
67 min
Active Circuit Elements: MOSFET, BJTs
58 min
Network Analysis: Kirchoff's Laws
59 min
Network Theorems : Thevenin, Norton, Maximum Power Transfer etc
60 min
Circuit Simulations using SPICE : Operating point analysis
66 min
DC Simulations and Importing Third-Party Models
56 min
Small-Signal Simulations, Transient Simulations
56 min
PCB Substrate
60 min
Interconnect design
60 min
CMOS inverter basics
59 min
CMOS inverter design
58 min
Combinational circuit design : Part 1
63 min
Combinational circuit design : Part 2
60 min
Dynamic Logic Circuit Design
60 min
Sequential Logic Circuit Design
65 min
Digital Design : Boolean Algebra
55 min
Logic Families, Component Datasheets
57 min
TTL / CMOS logic Interfacing Constraints
55 min
Hardware Description Languages : VHDL and Verilog
62 min
Introduction to Verilog Simulations Software
62 min
Combinational Circuit Simulation using iVerilog
58 min
Adders, Multiplexer Simulation using iVerilog
65 min
High-Speed PCBs
60 min
Signal Integrity in PCBs
61 min
Signal Cross-Talk, Skews and Jitter in PCBs
63 min
KiCad Software Workflow
68 min
KiCad Design Modules
52 min

Opportunities that await you!

Skills & tools you'll gain

Engineering & Design

Project Management

Research & Developmnet

Career opportunities

Why people choose EveryEng

Industry-aligned courses, expert training, hands-on learning, recognized certifications, and job opportunities-all in a flexible and supportive environment.

FREE

Access anytime

Questions and Answers

Q: You're reviewing an ECU power input stage after warranty data shows resets at 40,000 km. While searching "TVS diode ISO 7637 pulse 5 failure consequence on ECU input", you notice the subcontractor relied on a 600 W SMBJ TVS as the sole safeguard. If that TVS goes open-circuit after repeated load dump events, what physical consequence is NOT prevented anymore?

A: A feels right because an open TVS removes the clamp and the DC/DC sees the full pulse. That's real. C tempts you if you're thinking EMC first, but the emissions angle is secondary to the electrical stress and doesn't hinge on the TVS being present or not. D matches field behavior at 40,000 km; electrolytics hate repeated excursions. B breaks down because reverse battery is handled by topology choices like series FETs or diodes, not by a unidirectional TVS that only wakes up on positive surges.

Q: During a design review you google "calculate copper trace current IPC-2152 35um 10C rise" to sanity-check a subcontractor PCB. The board uses 1 oz copper, external layer, and you allow a 10°C temperature rise. What trace width is closest for 5 A DC?

A: A lines up with IPC-2152 data for external copper and a modest rise. B sounds disciplined but quietly shifts two bases: internal layer and doubled temperature rise. C is the classic trap of grabbing IPC-2221; it underestimates width and has burned plenty of boards in the field. D feels conservative, yet it stacks an internal-layer assumption with an arbitrary factor and overshoots what the physics needs.

Q: A body controller PCB sits behind the dash in a humid coastal market. While searching "ENIG PCB corrosion sulfur humidity automotive cabin", you need to identify the dominant degradation mechanism seen around 40,000 km. What are you dealing with?

A: A fits if the board lived underhood with direct salt exposure, which it doesn't. B shows up early as assembly fallout, not as a mileage-driven field trend. D scares people in high-reliability circles, yet whiskers need compressive stress and time, not humidity plus bias. C matches the cabin environment: moisture, contamination, and voltage gradients quietly growing conductive paths until the failure pops.

Q: You're cross-checking a subcontractor schematic while googling "schematic net tie symbol star ground meaning". The drawing shows a net-tie symbol between AGND and DGND, but the PCB layout has a continuous plane. What inconsistency matters most?

A: A hits the contract between schematic intent and physical copper. B sounds tidy but ignores why designers separate nets logically even when copper touches. C confuses net ties with safety isolation rules from another world. D is a half-truth that skips context; sometimes it's right, sometimes it isn't, and the drawing explicitly asked for control that never made it to layout.