Phase Locked Loops
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Why enroll
Is this course for you?
You should take this if
- You work in Electronics & Instrumentation or Telecommunication
- You're a Electronics & Telecommunication / Electrical Engineering professional
- You have 3+ years of hands-on experience in this field
- You want to build skills in Engineering & Design, Research & Developmnet
You should skip if
- You're new to this field with no prior experience
- You need a different specialisation outside Electronics & Telecommunication
- You need live interaction with an instructor
Course details
Course suitable for
Key topics covered
Course content
The course is readily available, allowing learners to start and complete it at their own pace.
- Course Introduction and Motivation Part I39 min
- Course Introduction and Motivation Part II23 min
- Basic Operation of a Phase Locked Loop25 min
- Simple Implementation of a Phase Locked Loop16 min
- Input Output Characteristics of Basic PLL Blocks27 min
- Time Domain Analysis of a Simple PLL21 min
- Time Domain Versus Small Signal Analysis of a Simple PLL21 min
- Type and Order of PLL9 min
- Small Signal Analysis of Type-I/II/III PLLs for Phase Step, Frequency Step and Frequency Ramp30 min
- Frequency Acquisition Range for PLLs26 min
- Frequency Acquisition in Type-I PLLs32 min
- Frequency Acquisition Limits in Type-I PLLs18 min
- Frequency Acquisition in Type II PLLs16 min
- Frequency Acquisition Ranges in Type II PLLs with Ideal and Non Ideal Integrator37 min
- Frequency Domain Insight in Frequency Acquisition for Type II PLLs14 min
- Introduction to Clock Multipliers12 min
- Analog Phase Error Detectors: Part I35 min
- Analog Phase Error Detectors: Part II25 min
- Digital Phase Error Detectors: Part I32 min
- Digital Phase Error Detectors: Part II19 min
- Range Extension for Phase Error Detectors9 min
- Phase Frequency Detector31 min
- Digital Frequency Detector16 min
- Charge Pump PLL23 min
- Small Signal and Stability Analysis of Type II Order 2 Charge Pump PLL21 min
- Problems in Charge Pump PLL - Dead Zone in PFD13 min
- Problems in Charge Pump PLL - Reference Spur23 min
- Design Procedure for Type-II Order 3 Charge Pump PLL15 min
- Design Procedure for Charge Pump Clock Multiplier18 min
- Sources of Non-Linearities in CP-PLL: Part I32 min
- Sources of Non-Linearities in CP-PLL: Part II19 min
- Noise Analysis in CP-PLL: Part I31 min
- Noise Analysis in CP PLL: Part II43 min
- Noise Analysis in CP-PLL: Part III40 min
- Noise Simulations for CP-PLL Blocks16 min
- Introduction to Oscillators49 min
- Low-Swing Ring Oscillator: Part II15 min
- Large-Swing Ring Oscillator: Part I39 min
- Large-Swing Ring Oscillator: Part II23 min
- Large-Swing Ring Oscillator: Part III33 min
- Large-Swing Ring Oscillator: Part IV10 min
- Large-Swing Ring Oscillator: Part V43 min
- Supply Regulated VCO: Part I24 min
- Supply Regulated VCO: Part II33 min
- Supply Regulated VCO: Part III28 min
- Phase Noise in Ring Oscillators33 min
- Circuit level Design of PFD: Part I20 min
- Circuit level Design of PFD: Part II18 min
- Circuit level Design of PFD: Part III12 min
- Circuit level Design of Charge Pump: Part I31 min
- Circuit-level Design of Charge Pump: Part II13 min
- Circuit-level Design of Charge Pump: Part III12 min
- Circuit-level Design of Charge Pump: Part IV51 min
- Circuit-level Design of Charge Pump: Part V8 min
- Circuit-level Design of Charge Pump: Part VI39 min
- Circuit-level Design of Clock Frequency Divider36 min
- Techniques for Wide Frequency Range Clock Multiplier39 min
- Introduction to Digital PLL35 min
- Design of Time-to-Digital Converter38 min
- Small Signal Analysis of Digital PLL34 min
- Noise Analysis in Digital PLL38 min
- Analog/Digital Hybrid PLL: Part I37 min
- Analog/Digital Hybrid PLL: Part II52 min
- Course Summary15 min
- Phase Locked Loops3 min
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