VLSI Physical Design with Timing Analysis | EveryEng

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VLSI Physical Design with Timing Analysis

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830 min

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Team EveryEngMechanical Engineering

Electronics & Instrumentation

Electrical Engineering

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Why enroll

Participants join this course to gain practical, industry-relevant skills in VLSI Physical Design and Static Timing Analysis (STA), which are in high demand across semiconductor companies. The course helps learners understand the complete backend design flow, improve their job readiness, and build the confidence to work on real-world chip design projects. It is also an excellent choice for students and professionals preparing for VLSI design interviews or looking to transition into the semiconductor industry.

Your instructor

Team EveryEng

Engineer

Mechanical Engineering

22+ yrs experience·India

Is this course for you?

You should take this if

You work in Electronics & Instrumentation
You're a Electrical Engineering / Electronics & Telecommunication professional
You have 3+ years of hands-on experience in this field
You prefer self-paced learning you can revisit

You should skip if

You're new to this field with no prior experience
You need a different specialisation outside Electrical Engineering
You need live interaction with an instructor

Course details

This course on VLSI Physical Design with Timing Analysis provides a comprehensive understanding of the complete physical design flow used in modern semiconductor chip development. It covers the transformation of a synthesized netlist into a manufacturable chip layout while meeting performance, power, and area constraints. Learners will explore key stages such as floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. The course also explains Static Timing Analysis (STA), timing constraints, setup and hold violations, clock uncertainty, and timing optimization techniques. Practical insights into industry-standard physical design methodologies and timing closure strategies are included throughout the course. Students will gain an understanding of how to optimize chip performance while ensuring signal integrity and design reliability. Real-world design concepts and workflows help bridge the gap between theory and industry practice. By the end of the course, learners will be equipped with the knowledge required to work on VLSI backend design projects and prepare for careers in semiconductor physical design and timing analysis.

Source: IIT Roorkee July 2018 (NPTEL official) [Youtube Channel]

Course suitable for

Key topics covered

Introduction to VLSI Design
Introduction to VLSI Physical Design
Complexity Analysis for Algorithms
Graphs for Physical Design
Graph Searching Algorithms
Spanning Tree and Shortest Path Algorithms
Overview of Timing Analysis
Timing Arcs and Unateness
Delay Parameters of a Combinational Circuit
Delay Parameters of a Sequential Circuit
Timing Analysis in a Sequential Circuit
STA in Sequential Circuit with Clock Skew – I
STA in Sequential Circuit with Clock Skew – II
STA in Sequential Circuit with Clock Jitter
STA Considering OCV and CRPR (Setup Check)
STA Considering OCV and CRPR (Hold Check)
STA for Combinational Circuits – I
STA for Combinational Circuits – II
Introduction to Partitioning – I
Introduction to Partitioning – II
Partitioning Algorithms
Kernighan–Lin (KL) Algorithm
Fiduccia–Mattheyses (FM) Algorithm
Introduction to Floorplanning
Floorplanning Representations

Course content

The course is readily available, allowing learners to start and complete it at their own pace.

25 lectures13 hr 50 min

VLSI Physical Design with Timing Analysis
4 min
Introduction to VLSI Design
37 min
Introduction to VLSI Physical Design
30 min
Complexity Analysis for Algorithms
38 min
Graphs for Physical Design
39 min
Graph searching Algorithms
22 min
Spanning Tree and Shortest Path Algorithms
22 min
Overview of Timing Analysis
28 min
Timing Arcs and Unateness
50 min
Delay Parameters of a Combinational Circuit
37 min
Delay Parameters of a Sequential Circuit
37 min
Timing Analysis in a Sequential Circuit
35 min
STA in Sequential Circuit with Clock Skew – I
39 min
STA in Sequential Circuit with Clock Skew – II
46 min
STA in Sequential Circuit with Clock Jitter
31 min
STA considering OCV and CRPR (Setup check)
36 min
STA considering OCV and CRPR (Hold check)
28 min
STA for Combinational Circuits – I
46 min
STA for Combinational Circuits – II
27 min
Introduction to Partitioning – I
39 min
Introduction to Partitioning – II
29 min
Partitioning Algorithms
34 min
Kernighan – Lin (KL) Algorithm
27 min
Fidduccia-Mattheyeses(FM) Algorithm
28 min
Introduction to Floorplanning
41 min

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