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VLSI Design Flow: RTL to GDS banner
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VLSI Design Flow: RTL to GDS

VLSI Design Flow: RTL to GDS banner
Preview this course
Self-paced Advanced

VLSI Design Flow: RTL to GDS

4(1581)
5 enrolled
91 views
FREE
1008 min
Anytime
English
91 views
Team EveryEng
Team EveryEngMechanical Engineering
Electronics & Instrumentation Electronics & Telecommunication
  • Lifetime access
  • Certificate of completion
  • Anytime Learning
  • Learn from Industry Expert
Volume pricing for groups of 5+

Why enroll

Participants join this course to understand the complete VLSI design flow from RTL to GDSII using industry-standard methodologies. It helps learners build practical knowledge of digital ASIC design, physical design, and EDA tools. The course is ideal for students, fresh graduates, and professionals looking to develop job-ready VLSI skills and prepare for careers in the semiconductor industry.

Your instructor

Team EveryEng

Team EveryEng

Engineer

Mechanical Engineering

22+ yrs experience·India

159Courses
43Articles
4.8kLearners
4Avg rating
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Is this course for you?

You should take this if

  • You work in Electronics & Instrumentation
  • You're a Electronics & Telecommunication / Electrical Engineering professional
  • You have 3+ years of hands-on experience in this field
  • You prefer self-paced learning you can revisit

You should skip if

  • You're new to this field with no prior experience
  • You need a different specialisation outside Electronics & Telecommunication
  • You need live interaction with an instructor

Course details

This course provides a comprehensive introduction to the complete VLSI Design Flow, covering every stage from Register Transfer Level (RTL) design to GDSII (Graphic Data System II) generation for chip fabrication. Learners will understand how digital integrated circuits are transformed from hardware descriptions into manufacturable layouts using industry-standard methodologies. The course explains key concepts such as RTL coding, logic synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, timing analysis, physical verification, and sign-off. It also introduces the tools and techniques used in modern ASIC design to optimize performance, power, and area (PPA). Through practical examples and real-world design workflows, participants gain insight into the complete backend implementation process. Whether you are a student or an aspiring VLSI engineer, this course builds a strong foundation in digital chip design and physical design concepts. By the end of the course, learners will have a clear understanding of the end-to-end VLSI design cycle and the steps required to convert an RTL design into a fabrication-ready GDSII layout.

Source: NPTEL-NOC IITM [ Youtube Channel]

Course suitable for

Key topics covered

  • Basic Concepts of Integrated Circuit - I

  • Basic Concepts of Integrated Circuit - II

  • Overview of VLSI Design Flow - I

  • Overview of VLSI Design Flow - II

  • Tutorial 1

  • Overview of VLSI Design Flow - III

  • Overview of VLSI Design Flow - IV

  • Overview of VLSI Design Flow - V

  • Overview of VLSI Design Flow - VI

  • Introduction to TCL

  • Hardware Modeling: Introduction to Verilog - I

  • Hardware Modeling: Introduction to Verilog - II

  • Functional Verification using Simulation

  • High-Level Synthesis using Bambu - Tutorial 3

  • RTL Synthesis - Part I

  • RTL Synthesis - Part II

  • Logic Optimization - Part I

  • Simulation-Based Verification using Icarus

  • Power Analysis

  • Power Optimization

  • Basic Concepts of DFT

  • Scan Design Flow

  • Power Analysis using OpenSTA

  • Automatic Test Pattern Generation (ATPG)

  • Built-in Self Test (BIST)

Course content

The course is readily available, allowing learners to start and complete it at their own pace.

25 lectures16 hr 48 min
  1. Basic Concepts of Integrated Circuit - I
    48 min
  2. Basic Concepts of Integrated Circuit - II
    37 min
  3. Overview of VLSI Design Flow - I
    47 min
  4. Overview of VLSI Design Flow - II
    46 min
  5. Tutorial 1
    10 min
  6. Overview of VLSI Design Flow - III
    43 min
  7. Overview of VLSI Design Flow - IV
    54 min
  8. Overview of VLSI Design Flow - V
    59 min
  9. Overview of VLSI Design Flow - VI
    28 min
  10. Introduction to TCL
    10 min
  11. Hardware Modeling: Introduction to Verilog-I
    46 min
  12. Hardware Modeling: Introduction to Verilog-II
    48 min
  13. Functional Verification using Simulation
    64 min
  14. High-level synthesis using Bambu - Tutorial 3
    7 min
  15. RTL Synthesis- Part I
    55 min
  16. RTL Synthesis- Part II
    35 min
  17. Logic Optimization: Part I
    70 min
  18. Simulation-based Verification using Icarus
    15 min
  19. Power Analysis
    47 min
  20. Power Optimization
    37 min
  21. Basic Concepts of DFT
    51 min
  22. Scan Design Flow
    42 min
  23. Power Analysis using OpenSTA
    17 min
  24. Automatic Test Pattern Generation (ATPG)
    47 min
  25. Built-in Self Test (BIST)
    45 min

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