Fabrication of Silicon VLSI Circuits using the MOS technology | EveryEng

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Fabrication of Silicon VLSI Circuits using the MOS technology

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1870 min

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Electronics & Instrumentation

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Participants join this course to clearly understand how integrated circuits are manufactured and how modern chips are scaled using Moore’s Law. The course helps them learn how scaling affects performance, power, and cost of ICs in real-world applications. It also gives insight into industry challenges and economics, making it valuable for students and professionals looking to build strong fundamentals and improve career opportunities in electronics and semiconductor fields.

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5+ yrs experience·India

Is this course for you?

You should take this if

You work in Electronics & Instrumentation
You're a Electronics & Telecommunication professional
You have 3+ years of hands-on experience in this field
You want to build skills in Engineering & Design

You should skip if

You're new to this field with no prior experience
You need a different specialisation outside Electronics & Telecommunication
You need live interaction with an instructor

Course details

This course explains how integrated circuits (ICs) are manufactured, starting from raw materials and moving step by step to finished chips using processes such as photolithography, etching, doping, and material layering. It introduces Moore’s Law and explains how transistor scaling has driven improvements in performance, speed, and power efficiency over time. Learners will understand the basic principles of scaling and why smaller feature sizes lead to more powerful and energy-efficient ICs. The course also discusses the physical and technological limits of scaling, including heat issues, quantum effects, and increasing manufacturing complexity. It explains how design decisions and fabrication techniques influence chip performance, reliability, and yield. Special focus is given to the economics of IC production, showing how technology nodes, production volume, and yield impact chip cost. Learners will see why advanced ICs are more expensive as equipment and process requirements grow. Real-world examples are used to show how industry balances performance, cost, and manufacturing challenges. By the end of the course, participants gain a clear understanding of both the technical and economic aspects of IC processing. Overall, the course provides a strong foundation in how modern integrated circuits are made, scaled, and priced

Source: nptelhrd [Youtube Channel]

Course suitable for

Key topics covered

Introduction Micro to Nano A Journey into Intergrated Circuit Technology
Introduction Micro to Nano A Journey into Intergrated Circuit Technology.
Crystal Properties and Silico Growth
Crystal Properties and Silico Growth contd.
IC Fab Labs and Fabrication of IC
Diffusion
Diffusion ( cont.)
Solid State Diffusion
Solid State Diffusion ( cont.)
Solid State Diffusion ( cont.).
Thermal Oxidation of Silicons
Thermal Oxidation of Silicons.
Thermal Oxidation of Silicons..
Thermal Oxidation of Silicons (cont.)
Thermal Oxidation of Silicons (cont.)..
Lithography
Lithography I
Lithography II
ION Implantation
ION Implantation .
ION Implantation & Silicon IC Processing Flow for CMOS Technology
ION Implantation & Silicon IC Processing Flow for CMOS Technology..
Silicon IC Processing Flow for CMOS Technology
Thin Film Deposition
Thin Film Deposition.

Course content

The course is readily available, allowing learners to start and complete it at their own pace.

25 lectures31 hr 10 min

Introduction Micro to Nano A Journey into Intergrated Circuit Technology
78 min
Introduction Micro to Nano A Journey into Intergrated Circuit Technology.
69 min
Crystal Properties and Silico Growth
74 min
Crystal Properties and Silico Growth contd.
77 min
IC Fab Labs and Fabrication of IC
79 min
Diffusion
74 min
Diffusion ( cont.)
75 min
Solid State Diffusion
76 min
Solid State Diffusion ( cont.)
84 min
Solid State Diffusion ( cont.).
77 min
Thermal Oxidation of Silicons
50 min
Thermal Oxidation of Silicons.
79 min
Thermal Oxidation of Silicons..
74 min
Thermal Oxidation of Silicons (cont.)
77 min
Thermal Oxidation of Silicons (cont.)..
73 min
Lithography
75 min
Lithography I
80 min
Lithography II
92 min
ION Implantation
74 min
ION Implantation .
71 min
ION Implantation & Silicon IC Processing Flow for CMOS Technology
75 min
ION Implantation & Silicon IC Processing Flow for CMOS Technology..
80 min
Silicon IC Processing Flow for CMOS Technology
71 min
Thin Film Deposition
74 min
Thin Film Deposition.
62 min

Opportunities that await you!

Skills & tools you'll gain

Engineering & Design

Career opportunities

Why people choose EveryEng

Industry-aligned courses, expert training, hands-on learning, recognized certifications, and job opportunities-all in a flexible and supportive environment.

What learners say about this course

Kaushik Bhatt

May 3, 2026

Emphasis on maintainability in structural models aligned with how I think about long-lived systems. The walkthrough in Chapter 6 on modal damping, especially the footbridge TMD example with measured vs predicted frequencies, stuck with me; I mapped it to arch tradeoffs and obs in prod, it's close to real constraints. Mostly, I wasn't sold on the brief MATLAB-only detour; wished there was more on validating against field data or railtransport vibration cases. Between meetings, the time spent felt justified, and I've already sketched notes I'd turn into a PR if this were a repo.

Alfred Tawiah Teaching Asistant

May 3, 2026

The ADMM walkthrough in Section 5, tuning rho on a lasso example, bridged theory to prod constraints and mirrored a repo PR I've seen. It's applicable to infra and CI, but wasn't sold on the convergence proofs pacing; wished more on stochastic methods at higher RPS.

Arshad Khan dev

May 3, 2026

Chapter 7’s Hertzian contact worked through the pressure distribution then mapped to an FEA check stuck with me; it bridged the continuum math to how I sanity-check stresses in prod arch. It's advanced and mostly hits, but I wasn't sold on the brief finite strain section—wished there was more on Ogden vs Neo-Hookean past elastic.

Sarra DEBBACHE

May 3, 2026

The labs had a way of exposing some bad habits, especially around treating equations as math instead of constraints on a system. In Lab 4 on internal pipe flow, the step where you nondimensionalize before touching the solver stuck; my first PR in the repo failed CI because I ignored the CFL limit and RPS blew up, which felt uncomfortably like prod. The section on boundary layers and the Blasius similarity solution was practical, tying assumptions back to arch choices rather than hand-wavy derivations. It's advanced and mostly aimed at people who already live near infra, but a bit more on turbulence modeling choices beyond k‑epsilon would’ve helped. Some labs ran long, and the obs guidance could be tighter. i don’t usually forward courses around, but this one got shared.

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Questions and Answers

Q: You're reviewing a mask set and process traveler because "gate oxide thickness spec mismatch between mask drawing and process sheet" keeps coming up in the NCR log. The poly gate mask notes tox = 7.5 nm nominal, ±0.5 nm. The oxidation step in the traveler calls out a dry O2 growth targeting 8.0 nm with ellipsometry control at ±3%. No rework step is defined. What do you sign off as the correct action before rerunning wafers?

A: The 0.5 nm delta is the trap. At sub‑10 nm oxides, a 6–7% thickness shift moves Vt by tens of millivolts, enough to blow corner coverage. Two documents defining different nominal values is a configuration control failure, not a process tweak problem. ISO-style change control applies even in a fab: stop, reconcile intent, then proceed. Splitting lots or tightening SPC doesn't fix an undefined requirement.

Q: You're checking a device physics calc because "how to calculate MOS capacitor threshold voltage from doping and oxide thickness" is what the junior wrote in the margin. For an nMOS on p‑type silicon: NA = 5×10^16 cm⁻³, tox = 10 nm, Qox negligible, φms = 0. Work function difference ignored. εox = 3.45×10⁻¹³ F/cm. What Vt do you expect at 300 K?

A: The hard number is 2φF. For NA = 5×10^16 cm⁻³, φF ≈ 0.36 V, so 2φF ≈ 0.72 V. Cox from 10 nm oxide is ~3.45×10⁻⁷ F/cm², giving a depletion term that pulls Vt down to the mid‑0.4 V range when Qox is zeroed. Ignoring φF or over‑weighting oxide thickness are classic slips.

Q: Process engineering asks you for a sanity check because "estimate junction depth after thermal diffusion back of envelope" is blocking a sign‑off. Boron diffusion at 1000 °C for 30 minutes, constant source, D ≈ 3×10⁻¹⁴ cm²/s. What's the right order of magnitude for junction depth?

A: The anchor is √(Dt). Thirty minutes is ~1.8×10³ s, so Dt ≈ 5×10⁻¹¹ cm² and √(Dt) ≈ 7×10⁻⁶ cm, or 0.07 µm. Junction depth for constant source is a few multiples of that, landing in the few‑tenths micron band. Answers in nanometers or multi‑microns miss the scale by an order.

Q: Facilities flags a concern during audit prep because "ISO 14644 cleanroom particle limits for VLSI fabrication" keeps getting misquoted. You're running a Class 5 (ISO) lithography bay. Why does the standard force continuous monitoring rather than periodic particle counts?

A: The tight boundary is defect density versus yield. At advanced nodes, a short particle spike during coat or expose maps directly to random killer defects. Periodic sampling averages that away. The standard pushes continuous monitoring to catch transient events that have irreversible electrical impact, not for cost or convenience.