System Design Through VERILOG | EveryEng

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Self-paced Advanced

System Design Through VERILOG

5(3)

3 enrolled

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FREE

471 min

Anytime

English

313 views

Telecommunication

Electronics & Telecommunication

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Why enroll

Learn Digital Hardware Design with Verilog To gain a solid foundation in Verilog HDL, which is essential if you want to design digital circuits or program FPGAs. Academic Coursework Support Students in Electronics & Communication, Electrical Engineering, or Computer Engineering use this as supplementary material alongside formal coursework. Practical Skills for FPGA/ASIC Development. Understanding Verilog is a key step toward real-world hardware design — on FPGAs or ASICs — and this playlist teaches the syntax and modeling needed before moving to synthesis tools. Preparation for Projects & Internships Those preparing for internships or projects in embedded systems or digital design leverage this to build hands-on Verilog skills.

Your instructor

Vaibhav Raj

student

India

Is this course for you?

You should take this if

You work in Telecommunication
You're a Electronics & Telecommunication / Electrical Engineering professional
You have 3+ years of hands-on experience in this field
You prefer self-paced learning you can revisit

You should skip if

You're new to this field with no prior experience
You need a different specialisation outside Electronics & Telecommunication
You need live interaction with an instructor

Course details

The main objective of this playlist is to teach Verilog HDL for digital system design starting from the basics of Verilog syntax and operators to modeling digital circuits and understanding how hardware designs are described textually for simulation and synthesis into real hardware. The course appears to be structured like a university lecture series, likely intended for undergraduate students learning digital logic design, system design, or VLSI/FPGA programming.

SOURCE - NPTEL[YOUTUBE]

Course suitable for

Key topics covered

1. Verilog Operators and Modules

2. Verilog Ports, Data types and Assignments

3. Half adder, full adder and ripple carry adder

4. Multiplier and comparator

5.Decoder, encoder and multiplexer

6. Decoder, encoder and multiplexer

7. Review of flip-flops

Course content

The course is readily available, allowing learners to start and complete it at their own pace.

10 lectures7 hr 51 min

Lec 1: Verilog Operators and Modules
38 min
Lec 2: Verilog Ports, Data types and Assignments
40 min
Lec 3: Basics of gate level modeling
48 min
Lec 4: Half adder, full adder and ripple carry adder
50 min
Lec 5: Parallel adder/subtractor
50 min
Lec 6: Multiplier and comparator
52 min
Lec 7: Decoder, encoder and multiplexe
53 min
Lec 8: Demultiplexer, read only memory
50 min
Lec 9: Review of flip-flops
42 min
Lec 10: Verilog modeling of flip-flops
48 min

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Questions and Answers

Q: You're migrating a protection path controller from SDH glue logic into FPGA fabric and searching "verilog clock domain crossing protection path enable glitch". The enable crosses from a 19.44 MHz recovered clock into a 125 MHz system clock. Latency budget is 3 cycles max. Which implementation best fits the duty and constraints?

A: Pick the wrong structure and you either metastability‑bomb the fabric or blow the latency budget, tripping protection during a switchover. A 2‑FF synchronizer plus pulse conditioning accepts that the signal is an event, not data, and keeps latency bounded. The FIFO preserves data but adds unnecessary state and timing closure pain at 125 MHz. The async set FF invites metastable release. The handshake is clean but adds unbounded cycles when the far side stalls.

Q: While debugging false hits, you Google "estimate metastability MTBF two flip-flop synchronizer 125MHz". Data sheet gives τ = 50 ps, T0 = 0.1 ns. Source clock is 19.44 MHz, destination 125 MHz. Order‑of‑magnitude MTBF?

A: Get this wrong and you either overdesign with FIFOs everywhere or ship a box that trips once a week. MTBF grows exponentially with available resolution time; with ~1 ns slack, exp(T/τ) is enormous. The clock rates contribute linearly and don’t kill the exponent. Two FFs don’t make it infinite, but they push failures into geological time at these numbers.

Q: You're reviewing a reset scheme and search "verilog async reset deassertion hazard fpga". The global reset is async assert, sync deassert. The sync logic fails. What does this safeguard NOT protect you from?

A: Assume the wrong coverage and you’ll chase ghosts after FAT when hardware disagrees with sim. Async assert doesn’t guard against metastability at the assertion edge; only deassertion is synchronized. The scheme does help align release, reduce CDC misuse of reset, and limit sim/silicon mismatch on exit from reset.

Q: Post‑migration, counters drift only in hardware. Sim is clean. You search "verilog blocking vs nonblocking counter synthesis mismatch". What root cause fits all symptoms?

A: Pick the wrong culprit and you’ll keep re‑running STA while the bug ships. Blocking assignments in sequential logic can simulate fine but synthesize into logic that feeds itself within a cycle, showing drift only in silicon. The other options either fail sim as well or produce deterministic behavior that STA would flag.