VLSI Design Flow: RTL to GDS | EveryEng

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Self-paced Advanced

VLSI Design Flow: RTL to GDS

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750 min

Anytime

English

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Electronics & Instrumentation

Electronics & Telecommunication

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Why enroll

Participants join the VLSI Design Flow: RTL to GDS course to gain a clear and practical understanding of the complete chip design lifecycle, starting from RTL design and ending with GDSII tape-out. The course helps bridge the gap between academic concepts and real-world industry workflows by explaining how each stage of VLSI design—such as synthesis, floorplanning, placement, routing, timing analysis, and verification—fits together in an actual project. It equips learners with industry-relevant knowledge and terminology, making them better prepared for VLSI internships, jobs, and advanced studies, while building confidence in understanding how modern integrated circuits are designed and manufactured.

Your instructor

Vaibhav Raj

student

India

Is this course for you?

You should take this if

You work in Electronics & Instrumentation
You're a Electronics & Telecommunication / Electrical Engineering professional
You have 3+ years of hands-on experience in this field
You prefer self-paced learning you can revisit

You should skip if

You're new to this field with no prior experience
You need a different specialisation outside Electronics & Telecommunication
You need live interaction with an instructor

Course details

The VLSI Design Flow: RTL to GDS course provides a concise yet comprehensive overview of the complete ASIC design process, covering all major stages from RTL coding and logic synthesis to physical design and final GDSII generation. It explains key concepts, tools, and methodologies used in the semiconductor industry, helping learners understand how functional designs are transformed into manufacturable chips. The course focuses on building a strong conceptual foundation of both front-end and back-end VLSI design in a clear and industry-oriented manner.

Source : YouTube [NPTEL]

Course suitable for

Key topics covered

1. Logic Optimization

2. Formal Verification

3. Static Timing Analysis

4. Constraints

5. Technology Mapping

6. Timing-driven Optimization

7. Technology Library and Constraints

Course content

The course is readily available, allowing learners to start and complete it at their own pace.

19 lectures12 hr 30 min

VLSI Design Flow: RTL to GDS - Course Intro
10 min
Logic Optimization: Part II
69 min
Logic Optimization: Part III
33 min
Formal Verification-I
67 min
Logic Synthesis using Yosys
7 min
Formal Verification-II
34 min
Formal Verification-III
64 min
Formal Verification IV
34 min
Technology Library
67 min
Logic Optimization using Yosys
14 min
Static Timing Analysis- I
14 min
Static Timing Analysis- II
74 min
Static Timing Analysis- III
60 min
Static Timing Analysis using OpenSTA
14 min
Constraints I
54 min
Constraints II
38 min
Technology Mapping
30 min
Timing-driven Optimization
49 min
Technology Library and Constraints
18 min

Opportunities that await you!

Career opportunities

✎ Where this fits — what comes before, what comes next

Why people choose EveryEng

Industry-aligned courses, expert training, hands-on learning, recognized certifications, and job opportunities-all in a flexible and supportive environment.

What learners say about this course

Engineering Academy Engineer

Feb 26, 2026

Best Course I found ever

Engineering Academy Engineer

Feb 23, 2026

Great Explanation

Engineering Academy Engineer

Feb 9, 2026

Nice explanation

Engineering Academy Engineer

Feb 26, 2026

Best Course I found ever

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Questions and Answers

Q: You're closing timing before tapeout and searching "how to calculate setup slack from RTL to GDS timing report" while the foundry slot closes tonight; given a path with clock period 1.2 ns, clock uncertainty 80 ps, data path delay 0.93 ns, setup time 65 ps, and clock skew of +30 ps at the capture flop, what is the setup slack?

A: A would come from subtracting skew instead of adding it to the capture edge, overstating margin. B results if clock uncertainty is double-counted against the data path. C drops clock uncertainty entirely and treats setup as already embedded in library delay. D correctly computes slack as 1.2 ns − (0.93 ns + 0.065 ns) − 0.08 ns + 0.03 ns = 0.16 ns.

Q: Post-route signoff shows clean STA but silicon fails at high temperature only, and you're googling "RTL to GDS high temperature failure despite clean STA" to brief management before tomorrow's lot start; scan chains pass at room temp, functional logic misbehaves at 125°C—what's the most likely root cause?

A: A would show up as failures across temperatures and typically during scan shifting. B usually causes intermittent or pattern-specific failures even at room temperature. C would be caught before tapeout and wouldn't correlate with temperature. D explains temperature sensitivity because higher resistivity increases voltage drop, stretching delays beyond modeled margins.

Q: While reviewing reliability signoff and searching "electromigration vs TDDB failure mechanism in copper interconnect", the chip targets 7nm with Cu dual-damascene, high current density in M1, and long DC stress; what's the dominant degradation mechanism?

A: A dominates under high electric field across dielectrics rather than metal lines. B requires repeated temperature swings rather than steady DC stress. C applies to Al metallization and package-level exposure, not buried Cu. D matches sustained high current density in fine Cu lines where atom migration forms opens.

Q: ESD clamps are signed off and you're searching "what ESD protection does not protect against in CMOS ICs" after a field return shows latent failures months later; what risk does on-chip ESD protection NOT mitigate?

A: A is directly addressed by input clamps sized for HBM levels. B is covered by fast-triggering local protection networks. C is mitigated indirectly by robust pad structures and grounding. D is a reliability aging mechanism unrelated to transient discharge energy.