VLSI Design Flow: RTL to GDS

VLSI Design Flow: RTL to GDS

Vaibhav Raj

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Why enroll

Participants join the VLSI Design Flow: RTL to GDS course to gain a clear and practical understanding of the complete chip design lifecycle, starting from RTL design and ending with GDSII tape-out. The course helps bridge the gap between academic concepts and real-world industry workflows by explaining how each stage of VLSI design—such as synthesis, floorplanning, placement, routing, timing analysis, and verification—fits together in an actual project. It equips learners with industry-relevant knowledge and terminology, making them better prepared for VLSI internships, jobs, and advanced studies, while building confidence in understanding how modern integrated circuits are designed and manufactured.

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Career opportunities

Course content

The course is readily available, allowing learners to start and complete it at their own pace.

FULL COURSE

19 Lectures

750 min

VLSI Design Flow: RTL to GDS - Course Intro
Preview
10 min
Logic Optimization: Part II
69 min
Logic Optimization: Part III
33 min
Formal Verification-I
67 min
Logic Synthesis using Yosys
7 min
Formal Verification-II
34 min
Formal Verification-III
64 min
Formal Verification IV
34 min
Technology Library
67 min
Logic Optimization using Yosys
14 min
Static Timing Analysis- I
14 min
Static Timing Analysis- II
74 min
Static Timing Analysis- III
60 min
Static Timing Analysis using OpenSTA
14 min
Constraints I
54 min
Constraints II
38 min
Technology Mapping
30 min
Timing-driven Optimization
49 min
Technology Library and Constraints
18 min

Course details

The VLSI Design Flow: RTL to GDS course provides a concise yet comprehensive overview of the complete ASIC design process, covering all major stages from RTL coding and logic synthesis to physical design and final GDSII generation. It explains key concepts, tools, and methodologies used in the semiconductor industry, helping learners understand how functional designs are transformed into manufacturable chips. The course focuses on building a strong conceptual foundation of both front-end and back-end VLSI design in a clear and industry-oriented manner.

Source : YouTube [NPTEL]

Course suitable for

Electronics & Instrumentation
Electrical
Electronics & Telecommunication
Instrumentation

Key topics covered

1. Logic Optimization

2. Formal Verification

3. Static Timing Analysis

4. Constraints

5. Technology Mapping

6. Timing-driven Optimization

7. Technology Library and Constraints

Our Alumni Work At

Ex-Tata Steel , Precision Engineering Division , West Bengal university

Chittagong University Of Engineering And technology

ENGGENIOUS - (SAN Techno Mentors Private Limited)

Smt Kashibai Navale College of Engineering Pune

Govind Ballabh Pant Institute of Engineering and technology pauri garhwal

Pal college of technology and management

Paltech cooling towers and equipments limited

East Point College of Engineering and Technology

university of technology and applied science

Center of Skill Development for Employability and Entrepreneurship

Airbornics Defence And Space Private Limited

Why people choose EveryEng

Industry-aligned courses, expert training, hands-on learning, recognized certifications, and job opportunities—all in a flexible and supportive environment.

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Vaibhav Raj

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